Clocking-the computer system engine

In order to understand what clocking is and what role it plays in computing, we need to reveal the general building blocks of a computing system. This post provides a "programmer" high level view of systems and clocking. No terms regarding to electronics or electric circuits theory are used here. We focus on providing pure logic view of the system. To make it as short as possible, two crucial terms will be explained here: "System topology" and "Clock distribution".

System topology in a nutshell

Figure 1 below, depicts a scheme of a sample system. The components in this figure are organized in a horizontal tree alike structure.

Figure1: Sample topology of a computer system with once core

A few terms have to be defined:

1. Core-Consists of the CPU and internal components that are used tightly by the CPU to allow efficient operation
2. Bus-A "branch" on the system tree. In Figure1, there are external four buses that are also called "Peripheral buses".
3. Bridge-A buffer with some embedded logic that controls data transfer between devices residing on different buses, or between a device and the code block, or between buses that are not close to each other. In Figure 1, there are four bridges.
4. Root Bridge-A bridge that controls the data transfer between the core block and the buses/devices.  
5. Device-A "leaf" on the bus. Also called "Peripheral device". 
6. Clock-A sequence of periodic pulses. The core block and each device may perform a few concurrent operations in either the falling or rising or both edges of a one pulse.

Generally speaking, each one of the buses receives its own clock, and each device that resides on an individual bus, operates based on the clock provided to its hosting bus. The core block also receives a separate clock input.

Clock distribution schemes

The clock source may be external (such as a pulse generator) or one that resides on the board (such as Quartz crystal). Generally speaking, the Quartz crystal clock source provides a low frequency signal, which is not sufficient for normal mode operation of the device. On the other hand, the external clock source is controlled by the manufacturer, and must comply with the board limitations. Extreme high frequency clock may damage the board due to insufficient heat sustainability.

We will discuss two schemes: One that uses the clock source as it is, and the other one that transforms the low input clock frequency into high frequency one.

Direct clock input

Figure 2 below describes the clock signal distribution from the clock source to the devices.

Figure2: Sample system using constant direct clock source

The input clock graph is plotted at the top of the figure. The clock rate is defined by the number of time periods in one second. Each time period starts at the bottom of the falling edge of the previous pulse and terminates just before the current pulse falling edge. This rate is measured in Hertz units (Hz) and is called "Frequency".

So, if there are 6 periods in 1 second, than the frequency is 6 Hz and the period time is 1/6=0.16 seconds, or 166 millisecond.

This clock is provided as an input signal to the divide and split hardware component. The time period of the signal provided to node(bus) 1 is twice the period time of the original clock. Hence, since the frequency change is relatively opposite to the change of time period-it was reduced to half.

The same applies to node(bus) 2, but here, the frequency was divided by 1.5, and the time period was extended by 1.5.

So, the term "Divider" applies to the frequency and NOT to the time period.

Transformed clock input

There are two differences between Figure 3 below, and Figure 2:

1. The frequency of the input signal is very low. Actually, the frequency of the input signal at Figure 2 looks 4 times higher than the one plotted in Figure 3.
2. An additional frequency multiplying unit residing between the input clock and the divide and split unit.

But here is the main point - the clock frequency of the signal created by the multiplying unit is equal to the input signal frequency at Figure 2. And of course, the devices on nodes 1 and 2 still get clock frequencies equal to those in Figure 2.

Figure3: Sample system using a multiplying unit on constant clock source

So, why do we need this multiplying unit? There are a few answers:

1. Relying on the board's internal Quartz crystal as the clock source. That means reducing risk of overheating.
2. The multiplying unit is programmable. The software programmer can adjust its multiplying factors at any time with a few C code lines. 

Are there any pitfalls? The answer is yes. This is why:

1. The multiplying unit is a "self and fix" system, known in science as "negative feedback system". It means that there will always be a tiny deviation from the desired frequency.
2. This unit can be also manually turned on and off by the software programmer during operation life time. Turning it on, puts the whole system in an unstable state, since the clock rate has not been stabilized, yet. Fortunately, boards that support this multiplying unit, bypass it and make the board work with the original frequency till the output from the multiplying unit is stable. However, it is a time consuming process.

This multiplying unit is called PLL (Phase-locked loop) system.

PLL-The frequency multiplier

Figure 4 provides a block diagram of the PLL system.

Figure4: Conceptual PLL

The components from which this diagram consists are described below:

1. ClockIn - The frequency of the clock signal provided to the board, either by the Quartz crystal or by an external clock generator.
2. Feedback-The feedback clock generated by the Divider.
3. Phase detector-A unit that constantly subtract the frequency of Feedback from ClockIn and generates an error signal accordingly.
4. Pump-Adjusts the voltage provided to the VCO, based on the polarity (negative or positive) of the error signal.
5. NewV-The voltage produced by the pump.
6. VCO-Voltage controlled oscillator.Transforms NewV into a ClockOut.
7. ClockOut-This is the PLL clock that is internally provided to the buses(nodes), the CPU, and the Divider.
8. Divider-A programmable unit, that produces Feedback clock with a frequency, given by dividing the frequency of ClockOut by the value entered by the software programmer.  

So, how does the PLL work as a frequency multiplier? Let's look at Figure 5.

Figure5: PLL operation flowchart

The PLL is always looking for a stable ClockOut, and obviously - this is the desire of the system as well.
This stability is achieved whenever no error signal is generated.
At power up stage, there is no Feedback clock yet and the Phase detector will create a positive error signal. That will increase ClockOut. This clock goes through the Divider which generates a Feedback clock.
The Feedback clock's frequency  is either equal to or  smaller then the frequency of ClockOut, but it increases.
The process repeats until the frequencies of Feedback clock and ClockIn are equal, and no error signal is produced.

So, how does the software programmer take control on ClockOut?
The answer is simple. By adjusting the value of the Divider, the frequency of Feedback clock will immediately change, and an error signal will be produced by the phase detector. That will result in a cue of the whole frequency adjustment process, according to the flowchart.

Final note

The clock is the mechanism that allows the system to operate. It can be adjusted by the software programmer by writing a few C code lines.
Many posts in this blog assume that this subject is well understood.
Now you are ready to deal with programming of hardware components.